VLSI Patshala

RTL & Logic Design Engineer

About Me

Passionate about designing efficient, high-performance digital systems. I specialize in RTL (Register Transfer Level) design, logic design, and VLSI (Very Large Scale Integration) methodologies.

Technical Expertise

Languages: Verilog, SystemVerilog, VHDL, C/C++
Design: RTL Coding, FSM Design, FIFO Design
Protocols: APB, AHB, AXI, UART, SPI, I2C
Tools: Vivado, Design Compiler